The present invention relates to circuits for generating a voltage reference and in particular start-up circuits for generating voltage references using a current-mode bandgap reference.
The bandgap reference circuit is commonly used in integrated circuits for providing reference voltages to devices such as analogue to digital converters, voltage regulators, etc. Bandgap reference circuits provide references with reliable and accurate voltages even in devices where relatively low supply voltages are used. The trend in integrated circuits towards using ever lower supply voltages is so as to derive advantages in terms of increased speed and reduced power consumption. This need for operation at lower voltages leads to a number of issues which limit the ability of conventional voltage reference designs to operate. Traditional voltage-mode designs are unable to work at the lower supply voltages required. FIG. 1 illustrates a voltage-mode bandgap reference cell.
In the circuit shown in FIG. 1, two bipolar transistors Q1, Q2 are each used in a diode connected configuration. One of the transistors, Q2, is designed to be larger by a factor N than the other transistor Q1. Current is provided to the respective transistors Q1 and Q2 by two PMOS transistors MP1 and MP2. These PMOS transistors are arranged as current sources with the respective current that flows through them being controlled by an amplifier A1. Consequently, the currents flowing into the respective emitters of transistors Q1 and Q2 are the same as those flowing from the respective drains of transistors MP1 and MP2. The amplifier A1 is arranged to ensure that the voltages at nodes N1 and N2 are the same. As mentioned above, Q2 is a larger transistor than Q1 and so the current density in Q2 is lower than in Q1. As a result, the voltage across Q2 is lower than the voltage across Q1 due to the lower current density. As a further result, the base/emitter voltage difference between Q1 and Q2 appears across the resistor R1 and the current through R1 is determined according to this voltage difference. Consequently, the voltage VREFVM is determined according to the sum of the voltages across resistors R1 and R2 and the voltage on transistor Q2.
                                          V                          REF              ,              VM                                =                                    V                              Q                ⁢                                                                  ⁢                2                                      +                          V                              R                ⁢                                                                  ⁢                1                                      +                          V                              R                ⁢                                                                  ⁢                2                                                                                  =                                    V                              Q                ⁢                                                                  ⁢                2                                      +                                                            (                                                            V                                              Q                        ⁢                                                                                                  ⁢                        1                                                              -                                          V                                              Q                        ⁢                                                                                                  ⁢                        2                                                                              )                                                  R                  ⁢                                                                          ⁢                  1                                            ·                              (                                                      R                    ⁢                                                                                  ⁢                    1                                    +                                      R                    ⁢                                                                                  ⁢                    2                                                  )                                                                                  =                                    V                              Q                ⁢                                                                  ⁢                2                                      +                                          V                T                            ·                              ln                ⁡                                  (                  N                  )                                            ·                              (                                  1                  +                                                            R                      ⁢                                                                                          ⁢                      2                                                              R                      ⁢                                                                                          ⁢                      1                                                                      )                                                                    V              REF        ,        VM              =                  V                  Q          ⁢                                          ⁢          1                    +                        V          T                ·                  ln          ⁡                      (            N            )                          ·                              R            ⁢                                                  ⁢            2                                R            ⁢                                                  ⁢            1                              where: VQ1−VQ2=VT·ln(N); VT=k·T/q; k is Boltzmann's constant; T is the absolute temperature in degrees Kelvin; and q is the magnitude of electronic charge.
The voltage difference between transistors Q1 and Q2 has a positive temperature coefficient whereas the voltage across Q2 has a negative temperature coefficient. These temperature coefficients can be cancelled out by appropriate selection of the resistors R1 and R2. As a result, the voltage reference has a very low temperature dependency.
The circuit of FIG. 1 ideally operates at a stable operating point where current is flowing through the transistors Q1 and Q2. However, this circuit also has a second stable operating point where no current is flowing through the transistors Q1 and Q2. FIG. 2 shows the operational characteristics at nodes N1 and N2 of the circuit of FIG. 1.
The two trace lines in FIG. 2 represent the voltages produced at nodes N1 and N2 in response to the current being sourced by the respective transistors MP1 and MP2. Where the lines coincide, a stable operating point is defined. Consequently, it can be seen that the lines are coincident at zero operating current and at a current, in this particular example, of just over 3 μA, as indicated by the dashed line. This characteristic of having two stable operating points leads to a problem in starting the circuit. If the circuit is simply switched on then it is possible that it will simply remain in the stable zero current operating state. Consequently, the starting of these circuits can be problematic.
In order to start such a circuit correctly, a small start-up current can be injected at the correct node which is then usually enough to overcome the zero current state and lead the circuit towards the desirable stable operating point.
With the voltage-mode arrangement of FIG. 1, the reference voltage is around 1.25V and so the supply voltage must be at least 1.25V.
FIG. 3 shows a current-mode bandgap reference cell which is based upon the voltage-mode bandgap cell illustrated in FIG. 1. In this FIG. 3 arrangement, there is a further PMOS transistor MP3 to provide a current which is used to produce a reference voltage VREFCM across an additional resistor R4. Additional current paths are also introduced via repositioned resistors R2 and R3. These additional current paths provide that the current flowing through the PMOS transistors of the current mirror has a relationship to both VQ1 and VT.
            I              MP        ⁢                                  ⁢        3              =                  I                  MP          ⁢                                          ⁢          2                    =                                    V                          Q              ⁢                                                          ⁢              1                                            R            ⁢                                                  ⁢            2                          +                                            V              T                        ·                          ln              ⁡                              (                N                )                                                          R            ⁢                                                  ⁢            1                                                                        V                          REF              ,              CM                                =                                                    I                                  MP                  ⁢                                                                          ⁢                  3                                            ·              R                        ⁢                                                  ⁢            4                                                        =                                                    V                                  Q                  ⁢                                                                          ⁢                  1                                            ·                                                R                  ⁢                                                                          ⁢                  4                                                  R                  ⁢                                                                          ⁢                  2                                                      +                                          V                T                            ·                              ln                ⁡                                  (                  N                  )                                            ·                                                R                  ⁢                                                                          ⁢                  4                                                  R                  ⁢                                                                          ⁢                  1                                                                                                  =                                                    R                ⁢                                                                  ⁢                4                                            R                ⁢                                                                  ⁢                2                                      ·                          (                                                V                                      Q                    ⁢                                                                                  ⁢                    1                                                  +                                                      V                    T                                    ·                                      ln                    ⁡                                          (                      N                      )                                                        ·                                                            R                      ⁢                                                                                          ⁢                      2                                                              R                      ⁢                                                                                          ⁢                      1                                                                                  )                                                                    =                                                    R                ⁢                                                                  ⁢                4                                            R                ⁢                                                                  ⁢                2                                      ·                          V                              REF                ,                VM                                                        
This current-mode topology has advantages over the voltage-mode arrangement of FIG. 1. However, the additional current paths through the repositioned resistors R2 and R3 result in additional stable operating points when there is no current flowing in the bipolar transistors. This is demonstrated in FIG. 4.
FIG. 4 shows a linear region where the current flowing from transistors MP1 and MP2 is flowing into the respective resistors R3 and R2, before any current begins to flow in the bipolar transistors Q1 and Q2. When no current is flowing in the bipolar transistors, the current through transistors MP1 and MP2 into resistors R2 and R3 (R2=R3) naturally leads to similar voltages on nodes N1 and N2 and so the circuit is stable. Consequently, in this range, a number of stable operating points can exist in addition to the desirable operating point. In order to deal with this problem, a robust way of starting up the circuit is required.
A number of different ways in which current-mode bandgap reference circuits can be started up have been proposed. However, many of these have drawbacks.
FIG. 5 shows a start-up circuit arrangement for a circuit such as that shown in FIG. 3. The circuit uses a PMOS transistor MP4 to feed current directly into node N1. When the circuit is initially powered on, there is no current flowing in the voltage reference cell formed by the transistors MP1, MP2, Q1, Q2 and resistors R1, R2, R3 and the amplifier A1. Node N1 will thus be close to VSS.
The additional bipolar transistor Q3 and the two resistors R6, R7 in conjunction with the current source CS2 generate a coarse voltage reference VC. This coarse reference voltage VC is compared, using a comparator C1, with the output reference voltage VREFCM. Whilst the voltage reference cell is not operating at the desired operating point, the current through MP1, MP2 and hence MP3 will be low. As a result, the voltage generated across R4, VREFCM, will be lower than the desired output. Whilst VC is greater than VREFCM, the comparator C1 keeps transistor MN5 turned on, which in turn, turns on the transistor MP4 so as to provide current into node N1. Thus, the start-up circuit continues to operate until the output VREFCM exceeds some predetermined threshold. However, this circuit fails to link the operating point of the additional bipolar transistor Q3 to the operating point of the bipolar transistors Q1 and Q2 in the bandgap reference cell. The current source biasing Q3 does not have any feedback from the voltage reference cell. Therefore the operating conditions of Q3 are not linked to those of Q1 and Q2. That means that even if Q3 is biased properly, there is a possibility that Q1 and Q2 are not. Thus again, the circuit does not reliably guarantee start-up.
The circuit described above provides a way of providing a start-up capability to the bandgap reference cell, but in the example above the proper start-up of the voltage reference is not guaranteed. There is therefore a need for a start-up circuit which is better able to ensure that the bandgap reference cell has started operating correctly and is at or tending towards the desired operating point under all circumstances.
It is therefore an aim of the present invention to provide a start-up circuit which will continue to operate until the bandgap reference cell is at or sufficiently close to a desired operating point before turning off. This can be achieved by ensuring that the start-up circuit is only turned off after current has started to flow in the bipolar transistors of the bandgap reference. This means that on the traces shown in FIG. 4, the voltage and currents have passed beyond the initial ramp i.e. the linear region, and away from the undesirable operating points associated with zero current in the bipolar transistors.
However, it is generally difficult to monitor the current through bipolar transistors formed on a substrate fabricated using a CMOS process. FIG. 6 shows a section of a substrate showing how a bipolar transistor is typically formed in such a substrate. A well of N-type material is produced in the P-type substrate. A P-type region is then formed in the N-type well. As shown in FIG. 6, the adjacent PNP layers form a parasitic PNP bipolar device which can be used as the basis for a bandgap reference circuit. However, because the collector of the transistor is formed by the substrate, it is difficult to measure the device collector current. Current flowing through the bipolar device passes into the substrate and so cannot be differentiated from other currents flowing into the substrate without isolating the bipolar collector from the rest of the substrate. Additionally, measuring the current through the bipolar device is difficult without disturbing the operation of the voltage reference cell.